EE 312: Integrated Circuit Fabrication Laboratory

Course Description

Fabrication, simulation, and testing of a submicron CMOS process. Students will be learning practical aspects of IC fabrication through experiments in the cleanroom including silicon wafer cleaning, photolithography, etching, oxidation, diffusion, ion implantation, chemical vapor deposition, physical sputtering, and electrical testing. Students also simulate the CMOS process using process simulator Sentaurus of the structures and electrical parameters that should result from the process flow. Cleanroom work will be performed in the Stanford Nanofabrication Facility (SNF). Preference to students pursuing doctoral research program requiring SNF facilities. Enrollment limited to 12. Prerequisites: EE 212, EE 216, and consent of instructor. Please fill out this form to apply by December 20th, 2024: https://forms.gle/FY8YFcnu3Xasugra8